KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 35

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

The format for ConfigPara
November 2005
Micrel Confidential
Bit
15
14
13
12
11
10
9
8-2
1
0
Bit Name
Reserved
NO_SRST
Reserved
PME_D2
PME_D1
D2_SUP
D1_SUP
Reserved
Clock_Rate
ASYN
m is shown in Table 10.
_8bit
Table 10. ConfigParam Word in EEPROM Format
Reserved
No Soft Reset
When this bit is set, indicates that KSZ8841M transitioning from D3_ho
D0 because of PowerState commands do not perform an internal reset
Configuration Context is
the D0 Initialize
required to preserve Configuration Context beyond writing the PowerState
bits.
When this bit is clear, KSZ8841M performs an internal res
transitioning f
Configuration Context is lost when performing the soft reset. Upon
trasition from the D3_hot to the D0 state, full reinitialization sequence i
needed to return the device to D0 Initialized.
R
sy
with only PME context preserved if PME is supported and enabled.
This bit is load
PME Support D2
When this bit is set, the KSZ8841M asserts PME event (pin 14) when the
KSZ8841M is
does not assert PME e
This bit is loaded to bit 1
PME Support D1
When this bit is set, the KSZ8841M asserts PME event (pin 14) when the
KSZ8841M is in D1 state and PME_EN is set. Otherwise, the KSZ8841M
does not assert PME event when the KSZ8841M is in D1 state.
This bit is loaded to bit 12 of PMCR register.
D2 Support
When this bit is set, the KSZ8841M supports D2 power state. This bit is
loaded to bit 10 of PMCR register.
D1 Support
When this bit is set, the KSZ8841M supports D1 power state. This bit is
loaded to bit 9 of PMCR register.
0: 125 MHz
1: 25 MHz
Note: At power up, this chip operates on 125 MHz clock. The internal
frequency can be dropped to
Async 8-bit bus select
1= bus is configured for
0= bus is configured for
This bit is loaded to bit 0
(32-bit width, KSZ8841-3
Description
Reserved.
Reserved.
Internal clock rate selection
egardless of this bit, devices that transition from
stem or bus segment reset will return to the device state D0 Uninitialized
rom D3_hot to D0 via software control of the PowerState bits.
in D2 state and PME_EN is set. Otherwise, the KSZ8841M
ed to bit 3 of PMCS register
d state, no additional operating system intervention is
35
vent when the KSZ8841M is in D2 state.
16-bit w
8-bit wi
3 of PMCR register
preserved. Upon transition from the D3_hot to
of PMC
2MQL
25
, don’t care this bit setting)
dth
idth
MHz via the external EEPROM.
R register
D3_hot to D0 by a
et upon
KSZ8841-16/32 MQL/MVL
s
.
t to
Rev 1.3