KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 7

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Selection of Isolation Transformers ...............................................................................................................93
Selection of Reference Crystal........................................................................................................................93
Package Information ........................................................................................................................................94
Acronyms and Glossary ..................................................................................................................................96
List of Figures
Figure 1. KSZ8841M Functional Diagram ..................................................................................................................................................1
Figure 2. Standard – KSZ8841-16 MQL 128-Pin PQFP (Top View)........................................................................................................... 9
Figure 3. Option – KSZ8841-16 MVL 128-Pin PQFP (Top View) ............................................................................................................... 9
Figure 4. Standard – KSZ8841-32 MQL 128-Pin PQFP (Top View)......................................................................................................... 15
Figure 5. Option – KSZ8841-32 MVL 128-Pin PQFP (Top View) ............................................................................................................. 15
Figure 6. Typical Straight Cable Connection ............................................................................................................................................ 24
Figure 7. Typical Crossover Cable Connection ........................................................................................................................................ 24
Figure 8. Auto Negotiation and Parallel Operation ................................................................................................................................... 25
Figure 9. Mapping from the ISA, EISA, and VLBus to the KSZ8841M Bus Interface ............................................................................... 31
Figure 10. KSZ8841M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections .................................................................................................... 31
Figure 11. PHY Port 1 Near-end (Remote) Loopback Path...................................................................................................................... 36
Figure 12. Asynchronous Cycle – ADSN = 0............................................................................................................................................ 82
Figure 13. Asynchronous Cycle – Using ADSN........................................................................................................................................ 83
Figure 14. Asynchronous Cycle – Using DATACSN ................................................................................................................................ 84
Figure 15. Address Latching Cycle for All Modes..................................................................................................................................... 85
Figure 16. Synchronous Burst Write Cycles – VLBUSN = 1..................................................................................................................... 86
Figure 17. Synchronous Burst Read Cycles – VLBUSN = 1 .................................................................................................................... 87
Figure 18. Synchronous Write Cycle – VLBUSN = 0................................................................................................................................ 88
Figure 19. Synchronous Read Cycle – VLBUSN = 0................................................................................................................................ 89
Figure 20. Auto Negotiation Timing .......................................................................................................................................................... 90
Figure 21. Reset Timing ........................................................................................................................................................................... 91
Figure 22. EEPROM Read Cycle Timing Diagram .................................................................................................................................. 92
Figure 23. 128-Pin PQFP Package .......................................................................................................................................................... 94
Figure 24. Optional 128-Pin LQFP Package ............................................................................................................................................ 95
November 2005
Micrel Confidential
Asynchronous Timing using Address Strobe (ADSN) ..................................................................................................................... 83
Asynchronous Timing using DATACSN.......................................................................................................................................... 84
Address Latching Timing for All Modes........................................................................................................................................... 85
Synchronous Timing in Burst Write (VLBUSN = 1) ......................................................................................................................... 86
Synchronous Timing in Burst Read (VLBUSN = 1) ......................................................................................................................... 87
Synchronous Write Timing (VLBUSN = 0) ...................................................................................................................................... 88
Synchronous Read Timing (VLBUSN = 0) ...................................................................................................................................... 89
Auto Negotiation Timing.................................................................................................................................................................. 90
Reset Timing................................................................................................................................................................................... 91
EEPROM Timing............................................................................................................................................................................. 92
7
KSZ8841-16/32 MQL/MVL
Rev 1.3