KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 66

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 19 Multicast Table Register 3 (0x06): MTR
Multicast table register 3.
Bank 19 Power Management Con
The following control and status reg
following table shows the register b
November 2005
Micrel Confidential
Bit
15-0
Bit
15
14-9
8
7-4
3
2
1-0
Default Value
0x0
Default Value
0
0x00
0
0x0
0
0
0x0
R/W
RW
R/W
RO
(W1C)
RO
RW
RO
RO
RO
RW
it fields.
trol and Status Register (0x08): PMCS
ister provides information on the KSZ8841M power management capabilities.
Description
MTR0 Mult
When the appropriate bit is set
hashing function is received without being filtered.
When the appropriate bit is cleared, the packet will drop
Note: When
all multicast addresses are received
Description
PME_Status
This bit indicates th
PME_Enable is set, the KSZ8841M also asserts the PMEN pin. This bit is cleared on
power-up reset or by write 1. It is not modified by either hardware or software reset.
When this bit is cleared, the KSZ8841M deasserts the PMEN pin.
Reserved.
PME_Enable
If this bit is se
PMEN pin is d
This bit is cleared on powe
Reserved.
No Soft Reset
If this bit is set (“1”), the KSZ8841M does not perform an internal reset when
transitioning from D3_hot to D0 because of PowerState commands. Configuration
context is preserved. Upon transition from D3_hot to the D0 Initialized state, n
additional operating system intervention is required to preserve configuration context
beyond writing the
If this bit is cleared (“0”), the KSZ8841M does perform an internal reset when
transitioning from D3_hot to D0 via software control of the PowerState bits.
Configuration
D3_hot to the D0 state, full reinitialization sequence is
D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus
segment reset will return to the device state D0 Uninitializ
preserved if PME is supported and enabled.
The value of this bit is loaded from the NO_SRST bit in the serial EEPROM.
Reserved.
Power State
This field is used to set the new power state of the KSZ8841M as well as to determine
its current power state. The definitions of the field values are:
00: D0 -> System is on and running
01: D1 -> Low-power state
10: D2 -> Low-power state
11: D3 (hot) -> System is off and not running
icast Table 3
the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR,
t, the KSZ8841M can assert the PMEN pin. Otherwise, assertion of the
context is lost when performing the soft reset. Upon transition from
isabled.
3
PowerState bits.
at the KSZ8841M has detected a power-management event. If bit
66
r-up reset and will be not modified by software reset.
, if the packet received with DA matches the CRC, the
regardless of the multicast table value.
needed to return the device to
.
ed with only PME context
KSZ8841-16/32 MQL/MVL
o
The
Rev 1.3