KSZ8841-16 Micrel Semiconductor, KSZ8841-16 Datasheet - Page 62

• Manufacturer Part Number: KSZ8841-16
• Description: Single-port Ethernet Mac Controller With Non-pci Interface
• Manufacturer: Micrel Semiconductor

Bank 18 Interrupt Enable Register (0x00): IER
This register enables the interrupts from the QMU and other sources.
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
W
This register is usually read by the h
are not cleared when read. The use
November 2005
Micrel Confidential
Bit
15
14
13
12
11
10
9
8
7
6-0
Bit
15
hen
the c
Default Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
Default Value
0x0
orresponding
en
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
R/W
RO
(W1C)
able
bit
is set, it caus
r has to write “1” to clear
Description
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit i
TXIE Trans
When this bit is set, the transmit interrupt is en
When this bit is reset, the transmit interrupt is disabled.
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
TXUIE Transmit Underrun Inte
When this b
When this bit is reset, the t
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interr
RXEIE Receive Early Receive Interrupt Enable
When this bit is s
When this bit is reset, the Early Receive interrupt is disabled.
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit i
When this bit is reset, the Transmit
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
RXEFIE Receive Error Frame Interrupt Enable
When this bit is set, the Receive error frame interrupt is enabled.
When this bi
Reserved.
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link
down, or link down to link up.
ost CPU and device drivers durin
mit Interrupt Enable
it is set, the transmit underrun interrupt is enabled.
t is reset, the Receive error frame interrupt is disabled.
s reset, the link change interrupt is disabled.
s set, the Transmit Process Stopped interrupt is enabled.
es the interrupt pin to be asserted.
et, the Early Receive interrupt is enabled.
62
ransmit underrun interrupt is disabled.
rrupt Enable
Process Stopped interrupt is disabled.
g interrupt service routine or polling. The register bits
abled.
upt is disabled.
KSZ8841-16/32 MQL/MVL
Rev 1.3