LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 13

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_2923_2925_0
Preliminary data sheet
www.DataSheet4U.com
6.6.3.1 ETM/ETB
6.6.4 Power supply pins
6.7.1 Clock architecture
6.7 Clocking strategy
The ETM provides real-time trace capability for deeply embedded processor cores. It
outputs information about processor execution to a trace buffer. A software debugger
allows configuration of the ETM using a JTAG interface and displays the trace information
that has been captured in a format that a user can easily understand. The ETB stores
trace data produced by the ETM.
The ETM/ETB module has the following features:
Table 6
Table 6.
The LPC2921/2923/2925 contains several different internal clock areas. Peripherals like
Timers, SPI, UART, CAN and LIN have their own individual clock sources called base
clocks. All base clocks are generated by the Clock Generator Unit (CGU0). They may be
unrelated in frequency and phase and can have different clock sources within the CGU.
The system clock for the CPU and AHB Bus infrastructure has its own base clock. This
means most peripherals are clocked independently from the system clock. See
for an overview of the clock areas within the device.
Within each clock area there may be multiple branch clocks, which offers very flexible
control for power-management purposes. All branch clocks are outputs of the Power
Management Unit (PMU) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. See
more details of clock and power control within the device.
Two of the base clocks generated by the CGU0 are used as input into a second,
dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate
the base clock for the USB controller and one base clock for an independent clock output.
Symbol
V
V
V
V
V
V
V
•
•
•
•
•
DD(CORE)
SS(CORE)
DD(IO)
SS(IO)
DD(OSC_PLL)
SS(OSC_PLL)
DDA(ADC3V3)
Closely tracks the instructions that the ARM core is executing.
On-chip trace data storage (ETB).
All registers are programmed through JTAG interface.
Does not consume power when trace is not being used.
THUMB/Java instruction set support.
shows the power supply pins.
Power supply pins
Description
digital core supply 1.8 V
digital core ground (digital core, ADC1/2)
I/O pins supply 3.3 V
I/O pins ground
oscillator and PLL supply
oscillator and PLL ground
ADC1 and ADC2 3.3 V supply
Rev. 00.01 — 24 October 2008
ARM9 microcontroller with CAN and LIN
LPC2921/2923/2925
© NXP B.V. 2008. All rights reserved.
Section 6.15
Figure 4
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