LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 9

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
6. Functional description
LPC2921_2923_2925_0
Preliminary data sheet
Pin name
P0[23]/IN2[7]/
PMAT2[5]/A19
TDI
www.DataSheet4U.com
Bidirectional Pad; Analog Port; Plain Input; 3state Output; Slew Rate Control; 5V Tolerant; TTL with Hysteresis; Programmable Pull Up /
Pull Down / Repeater.
USB pad, <tbd>.
Analog Pad; Analog Input Output.
Analog I/O pad, <tbd>.
LQFP100 pin assignment
6.1 Architectural overview
6.2 ARM968E-S processor
Pin
99
100
The LPC2921/2923/2925 consists of:
The LPC2921/2923/2925 configures the ARM968E-S processor in little-endian byte order.
All peripherals run at their own clock frequency to optimize the total system power
consumption. The AHB2APB bridge used in the subsystems contains a write-ahead buffer
one transaction deep. This implies that when the ARM968E-S issues a buffered write
action to a register located on the APB side of the bridge, it continues even though the
actual write may not yet have taken place. Completion of a second write to the same
subsystem will not be executed until the first write is finished.
The ARM968E-S is a general purpose 32-bit RISC processor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective controller
core.
Amongst the most compelling features of the ARM968E-S are:
[4]
•
•
•
•
•
•
[1]
An ARM968E-S processor with real-time emulation support
An AMBA multilayer Advanced High-performance Bus (AHB) for interfacing to the
on-chip memory controllers
Two DTL buses (an universal NXP interface) for interfacing to the interrupt controller
and the Power, Clock and Reset Control cluster (also called subsystem).
Three ARM Peripheral Buses (APB - a compatible super set of ARM's AMBA
advanced peripheral bus) for connection to on-chip peripherals clustered in
subsystems.
One ARM Peripheral Bus for event router and system control.
Separate directly connected instruction and data Tightly Coupled Memory (TCM)
interfaces
Description
Function 0 (default)
GPIO 0, pin 23
IEEE 1149.1 data in, pulled up internally
…continued
Rev. 00.01 — 24 October 2008
Function 1
ADC2 IN7
ARM9 microcontroller with CAN and LIN
LPC2921/2923/2925
Function 2
PWM2 MAT5
© NXP B.V. 2008. All rights reserved.
Function 3
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