LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 43

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LPC2925

Manufacturer Part Number
LPC2925
Description
(LPC2921 - LPC2925) ARM9 microcontroller
Manufacturer
NXP Semiconductors
Datasheet

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LPC2921_2923_2925_0
Preliminary data sheet
Fig 9.
www.DataSheet4U.com
400 kHz LP_OSC
CLOCK GENERATION UNIT (CGU0)
OSCLLLATOR
EXTERNAL
Block diagram of the CGU0 (see
FREQUENCY
MONITOR
There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a
crystal oscillator. See
LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for
BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog
timer). To prevent the device from losing its clock source LP_OSC cannot be put into
power-down. The crystal oscillator can be used as source for high-frequency clocks or as
an external clock input if a crystal is not connected.
Secondary clock generators are a PLL and seven fractional dividers (FDIV0..6). The PLL
has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted.
Configuration of the CGU0:
choice can be made from the primary and secondary clock generators according to
Figure
PLL
10.
DETECTION
clkout
clkout120
clkout240
CLOCK
Table 24
Rev. 00.01 — 24 October 2008
Figure
AHB TO DTL BRIDGE
for all base clocks)
9.
For every output generator generating the base clocks a
FDIV0
FDIV1
FDIV6
ARM9 microcontroller with CAN and LIN
LPC2921/2923/2925
OUT 0
OUT 1
OUT 2
OUT 3
OUT 11
002aae147
© NXP B.V. 2008. All rights reserved.
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_ICLK1_CLK
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