LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 20

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_2923_2925_0
Preliminary data sheet
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6.10.1 USB device controller
6.9.1 DMA support for peripherals
6.9.2 Clock description
6.10 USB interface
The GPDMA controls eight DMA channels with hardware prioritization. The DMA
controller interfaces to the system via two AHB bus masters, each with a full 32-bit data
bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can
be either big-endian or little-endian. Incrementing or non-incrementing addressing for
source and destination are supported, as well as programmable DMA burst size. Scatter
or gather DMA is supported through the use of linked lists. This means that the source
and destination areas do not have to occupy contiguous areas of memory.
The GPDMA supports the following peripherals: SPI0/1/2, UART0/1, and the
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external static memory, and flash memory.
The DMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see
Section
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic
configuration of the devices. All transactions are initiated by the Host controller.
The LPC2921/2923/2925 USB interface includes a device controller with on-chip PHY for
device. Details on typical USB interfacing solutions can be found in
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM.
The USB device controller has the following features:
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C0/1-interfaces. The GPDMA can access both embedded SRAM blocks, both TCMs,
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Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, the LPC2921/2923/2925 can enter the reduced
power mode and wake up on USB activity.
Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
6.7.2.
Rev. 00.01 — 24 October 2008
ARM9 microcontroller with CAN and LIN
LPC2921/2923/2925
Section
© NXP B.V. 2008. All rights reserved.
10.2.
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