LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 45

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
2.
LPC2921_2923_2925_0
Preliminary data sheet
Fig 11. PLL block diagram
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Generation of the main clock is restricted by the frequency range of the PLL clock input. See
input clock
6.15.2.2 PLL functional description
appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.
Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no
positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock
is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be
detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After
reset all clocks are assumed to be ‘non-present’, so the RDET status register will be
correct only after 32 BASE_PCR_CLK cycles.
Note that this mechanism cannot protect against a currently-selected clock going from
active to inactive state. Therefore an inactive clock may still be sent to the system under
special circumstances, although an interrupt can still be generated to notify the system.
Glitch-Free Switching:
switched glitch-free, both at the output generator stage and also at secondary source
generators.
In the case of the PLL the clock will be stopped and held low for long enough to allow the
PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch
will occur as quickly as possible, although there will always be a period when the clock is
held low due to synchronization requirements.
If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is
assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the
interface.
A block diagram of the PLL is shown in
analog section. This block compares the phase and frequency of the inputs and generates
the main clock
divider to create the output clock, or sent directly to the output. The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the analog section is also monitored by the lock detector to signal
when the PLL has locked onto the input clock.
CCO
2
. These clocks are either divided by 2 × P by the programmable post
bypass
Rev. 00.01 — 24 October 2008
Provisions are included in the CGU to allow clocks to be
MSEL bits
PSEL bits
/ 2PDIV
/ MDIV
Figure
ARM9 microcontroller with CAN and LIN
11. The input clock is fed directly to the
LPC2921/2923/2925
direct
Table
clkout
P23EN bit
32, Dynamic characteristics.
P23
© NXP B.V. 2008. All rights reserved.
clkout120
clkout240
clkout
002aad833
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