LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 26

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_2923_2925_0
Preliminary data sheet
www.DataSheet4U.com
6.12.4.1 Pin description
6.12.4.2 Clock description
6.12.5 Serial peripheral interface (SPI)
The UART is commonly used to implement a serial interface such as RS232. The
LPC2921/2923/2925 contains two industry-standard 550 UARTs with 16-byte transmit and
receive FIFOs, but they can also be put into 450 mode without FIFOs.
Remark: The LIN controller can be configured to provide two additional standard UART
interfaces (see
The UART pins are combined with other functions on the port pins of the
LPC2921/2923/2925.
Table 14.
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0-1), see
branch clock for power management. The frequency of all CLK_UARTx clocks is identical
since they are derived from the same base clock BASE_CLK_UART. The register
interface towards the system bus is clocked by CLK_SYS_PESS. The baud generator is
clocked by the CLK_UARTx.
The LPC2921/2923/2925 contains three Serial Peripheral Interface modules (SPIs) to
allow synchronous serial communication with slave or master peripherals.
The key features are:
Symbol
UARTx TXD
UARTx RXD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-byte receive and transmit FIFOs.
Register locations conform to 550 industry standard.
Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes.
Built-in baud rate generator.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
Master or slave operation
Each SPI supports up to four slaves in sequential multi-slave operation
Supports timer-triggered operation
Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock
Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep
Programmable choice of interface operation: Motorola SPI or Texas Instruments
Synchronous Serial Interfaces
Programmable data-frame size from 4 to 16 bits
Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
Serial clock-rate master mode: fserial_clk ≤ f
UART pins
Pin name
TXDx
RXDx
Section
Rev. 00.01 — 24 October 2008
Table 14
6.13.2).
Section
Direction
OUT
IN
shows the UART pins (x runs from 0 to 1).
6.7.2. Note that each UART has its own CLK_UARTx
Description
UART channel x transmit data output
UART channel x receive data input
ARM9 microcontroller with CAN and LIN
LPC2921/2923/2925
CLK(SPI)
/2
© NXP B.V. 2008. All rights reserved.
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