ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 101

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
10 Timing Characteristics for 2.7 V Operation
Table 88. Timing Requirements for PHIF Motorola Mode Signaling
Table 89. Timing Characteristics for PHIF Motorola Mode Signaling
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
99
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For
example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after
PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN
should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Abbreviated Reference
Abbreviated Reference
PB[7:0]
PBSEL
PSTAT
PRWN
PCSN
PDS
V
V
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
t45*
t46*
t47*
t48*
t51*
t52*
t154
t49*
t50*
t41
t42
t43
t44
Figure 24. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram
t45
t41
t43
t49
16-bit READ
PDS
PCSN to PDS
PRWN to PCSN Setup (valid to low)
PCSN to PRWN Hold (high to invalid)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN to PB Read 3-state (high to 3-state)
†
to PCSN Setup (valid to low)
†
Hold (high to invalid)
Parameter
Parameter
t42
t154
t50
t46
t44
(continued)
t47
t43
t51
Min
16-bit WRITE
—
—
0
Min
10
0
0
4
0
4
0
6
0
4
Lucent Technologies Inc.
Max
Max
12
—
8
—
—
—
—
—
—
—
—
—
—
February 1997
t44
t48
t52
Unit
Unit
5-4038 (C).a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns