ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 40

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
4 Hardware Architecture
PLL Programming Examples
The following section of code illustrates how the PLL would be initialized on powerup, assuming the following oper-
ating conditions:
The device would come out of reset with the PLL disabled and deselected.
pllinit: pllc = 0x2912
pllwait: if lock return
Programming examples which illustrate how to use the PLL with the various power management modes are listed
in Section 4.14.
Latency
The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the actual
switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be executed,
but it will be at the previous clock rate. Table 16 shows the latency times for switching between CKI-based and PLL-
based clocks. In the example given, the delay to switch to the PLL source is 1—4 CKO cycles and to switch back is
11—31 CKO cycles.
Table 16. Latency Times for Switching Between CKI and PLL-Based Clocks
Frequency Accuracy and Jitter
When using the PLL to multiply the input clock frequency up to the instruction clock rate, it is important to realize
that although the average frequency of the internal clock and CKO will have about the same relative accuracy as
the input clock, noise sources within the DSP will produce jitter on the PLL clock such that each individual clock
period will have some error associated with it. The PLL is guaranteed only to have sufficiently low jitter to operate
the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system.
V
The PLL has its own power and ground pins, V
form of a ferrite bead connected from V
a 0.01 F ceramic) from V
dation is subject to change and may need to be modified for specific applications depending on the characteristics
of the supply noise.
Note: For devices with the CMOS clock input option, the CKI2 pin should be connected to V
38
DDA
Switch from PLL-based clock
Switch to PLL-based clock
CKI input frequency = 10 MHz
Internal clock and CKO frequency = 50 MHz
VCO frequency = 100 MHz
Input divide down count N = 2 (Set Nbits[2:0] = 000 to get N = 2, as described in Table 36.)
Feedback down count M = 20 (Set Mbits[4:0] = 10010 to get M = 18 + 2 = 20, as described in Table 36.)
and V
pllc = 0xA912
call pllwait
pllc = 0xE912
goto start
goto pllwait
SSA
Connections
DDA
to V
/* Running CKI input clock at 10 MHz, set up counters in PLL */
/* Power on PLL, but PLL remains deselected */
/* Loop to check for LOCK flag assertion */
/* Select high-speed, PLL clock */
/* User's code, now running at 50 MHz */
SS
(continued)
. V
Latency (cycles)
DDA
SSA
Minimum
M/N + 1
to V
can be connected directly to the main ground plane. This recommen-
1
DDA
DD
and V
and two decoupling capacitors (4.7 F tantalum in parallel with
SSA
. Additional filtering should be provided for V
Latency (cycles)
M + M/N + 1
Maximum
N + 2
Lucent Technologies Inc.
SSA
February 1997
.
DDA
in the