ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 86

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
9 Electrical Characteristics and Requirements
9.1 Power Dissipation
Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power
dissipation listed is for a selected application. The following electrical characteristics are preliminary and are subject
to change.
Table 65. Power Dissipation and Wake-Up Latency
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
†
Lucent Technologies Inc.
Power Management Modes CKO = 40 MHz
ECCP Operation
Normal Operation
Normal Operation ioc = 0x0180
Standard Sleep, External Interrupt
Standard Sleep, External Interrupt
Sleep with Slow Internal Clock
Sleep with Slow Internal Clock
t
L
PLL Enabled
(Unused inputs at V
= PLL lock time (see Table 64).
CKI = 10 MHz CKO = 40 MHz
CKI = 40 MHz
PLL Disabled
PLL Disabled During Sleep
PLL Disabled During Sleep
CKI & CKO = 40 MHz
CKI & CKO = 0 MHz
PLL Enabled During Sleep
PLL Enabled During Sleep
alf[15] = 1, ioc = 0x0180
alf[15] = 1, ioc = 0x0180
alf[15] = 1, ioc = 0x0180
alf[15] = 1, ioc = 0x0180
Small Signal Enabled
Small Signal Enabled
powerc[15:14] = 01,
powerc[15:14] = 01,
Operating Mode
pllc = 0xFC0E
Small Signal
Small Signal
Small Signal
Small Signal
Small Signal
Small Signal
Small Signal
ioc = 0x0180
DD
or V
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
V
DD=
SS)
I/O Units ON, ECCP OFF
powerc[7:4,0] = 0x01
Typical Power Dissipation (mW)
28.1
93.7
96.3
0.17
2.75
96.7
99.3
14.0
16.3
16.5
18.9
3 V
0.7
3.7
3.3
6.1
I/O Units OFF, ECCP OFF
powerc[7:4,0] = 0xF1
91.2
93.7
0.17
2.75
94.2
96.7
12.0
11.2
14.0
3 V
9.3
0.5
3.5
2.9
5.5
—
(continued)
P
P
P
P
DSP1628 Digital Signal Processor
ECCP
DSP
DSP
SLEEP
During Wake State)
(PLL Not Used
5.0 s
5.0 s
3T*
3 V
3T*
—
—
—
—
—
—
—
—
—
—
—
Wake-Up Latency
During Wake State)
5.0 s + t
5.0 s + t
(PLL Used
3T* + tL
3T* + t
5.0 s
5.0 s
3T*
3 V
3T*
—
—
—
—
—
—
—
L †
†
L †
L †
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