ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 90

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
10 Timing Characteristics for 2.7 V Operation
10.2 Reset Circuit
The DSP1628 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below
V
shows two separate events:
Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.
* See Table 60, Recommended Operating Conditions.
* When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a
† See Table 62 for input clock electrical requirements.
Table 68. Timing Requirements for Powerup Reset and Chip Reset
Table 69. Timing Characteristics for Powerup Reset and Chip Reset
Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise,
Lucent Technologies Inc.
DD
3-state condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO
remains a free-running clock.
Abbreviated Reference
MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 12
Abbreviated Reference
OUTPUT
PINS *
RAMP
RSTB,
TRST
V
1. Chip reset at initial powerup.
2. Chip reset following a drop in power supply.
high currents may flow.
CKI †
DD
V
V
V
V
OH
OL
IH
t10
t11
IL
t146
t153
t8
t9
0.4 V
V
DD
t9
Figure 12. Powerup Reset and Chip Reset Timing Diagram
MIN
t146
RSTB Disable Time (low to 3-state)
RSTB Enable Time (high to valid)
RSTB and TRST Reset Pulse (low to high)
V
V
RSTB (low to high)
DD
DD
Ramp
MIN to RSTB Low
t10
t8
Parameter
Parameter
t153
t11
Small-signal
CMOS
(continued)
DSP1628 Digital Signal Processor
0.4 V
t9
t146
Min
—
—
Min
V
6T
2T
20
—
—
DD
MIN
Max
t10
100
100
t8
Max
10
54
—
—
—
5-4010 (C).a
t153
Unit
Unit
ns
ns
ms
t11
ns
ns
ns
s
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