ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 89

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
10 Timing Characteristics for 2.7 V Operation
10.1 DSP Clock Generation
* See Table 62 for input clock electrical requirements.
† Free-running clock.
‡ Wait-stated clock (see Table 38).
§ W = number of wait-states.
Table 66. Timing Requirements for Input Clock
* Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.
† Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
Table 67. Timing Characteristics for Input Clock and Output Clock
* T = internal clock period, set by CKI or by CKI and the PLL parameters.
87
Abbreviated Reference
Abbreviated Reference
1X CKI*
CKO
CKO
†
‡
t6a
V
V
V
V
t4
t5
t6
V
V
OH
OH
OL
OL
IH
IL
t1
t2
t3
t5
Clock Out High Delay
Clock Out Low Delay (high to low)
Clock Out Period (low to low)
Clock Out Period with SLOWCKI Bit
Set in powerc Register (low to low)
Clock In Period (high to high)
Clock In Low Time (low to high)
Clock In High Time (high to low)
Figure 11. I/O Clock Timing Diagram
t3
t1
EXTERNAL MEMORY CYCLE
Parameter
t2
t4
Parameter
W = 1
§
(continued)
t6, t6a
0.74
Min
—
—
T*
19.2 ns
Max
3.8
14
14
—
19.2 ns and 12.5 ns
Min
20
10
10
0.74
Min
—
—
T*
12.5 ns
Lucent Technologies Inc.
Max
—
Max
—
—
3.8
10
10
—
†
February 1997
Unit
Unit
5-4009 (C).a
ns
ns
ns
ns
ns
ns
s
*