ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 37
ds96-039wdsp
Manufacturer Part Number
ds96-039wdsp
Description
Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
Manufacturer
ETC-unknow
Datasheet
1.DS96-039WDSP.pdf
(114 pages)
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February 1997
4 Hardware Architecture
Table 15. JTAG Boundary-Scan Register
Note: The direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.
* Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
† Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will.
‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin.
Lucent Technologies Inc.
10—25
28—31
32—36
38—48
Cell
37
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
26
27
68
0
1
2
3
4
5
6
7
8
9
Type
OE
DC
OE
DC
DC
DC
DC
DC
OE
DC
DC
DC
DC
O
O
O
O
O
O
O
O
B
B
B
B
B
B
B
B
B
B
I
I
I
I
I
I
Controls cells 1, 27—31
CKO
RSTB
Controls cell 4
TRAP
STOP
IACK
INT0
Controls cells 6, 10—25, 49, 50, 78, 79
INT1
AB[0:15]
EXM
RWN
EROM, ERAMLO, ERAMHI, IO
DB[0:4]
Controls cells 32—36, 38—48
DB[5:15]
OBE1
IBF1
DI1
Controls cell 53
ILD1
Controls cell 55
ICK1
Controls cell 57
OCK1
Controls cell 59
OLD1
Controls cell 61
DO1
Controls cell 63
SYNC1
Controls cell 65
SADD1
Controls cell 67
DOEN1
Controls cell 69
†
Signal Name/Function
(continued)
Cell
100
101
102
103
104
69
70
71
72
73
74
75
76
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
77
—
Type
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DSP1628 Digital Signal Processor
—
O
O
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
I
OCK2/PCSN *
Controls cell 71
DO2/PSTAT *
Controls cell 73
SYNC2/PBSEL *
Controls cell 75
ILD2/PIDS *
Controls cell 77
OLD2/PODS *
IBF2/PIBF *
OBE2/POBE *
Controls cell 81
ICK2/PB0 *
Controls cell 83
DI2/PB1 *
Controls cell 85
DOEN2/PB2 *
Controls cell 87
SADD2/PB3 *
Controls cell 89
IOBIT0/PB4 *
Controls cell 91
IOBIT1/PB5 *
Controls cell 93
IOBIT2/PB6 *
Controls cell 95
IOBIT3/PB7 *
Controls cell 97
VEC3/IOBIT4 *
Controls cell 99
VEC2/IOBIT5 *
Controls cell 101
VEC1/IOBIT6 *
Controls cell 103
VEC0/IOBIT7 *
CKI
—
‡
Signal Name/Function
35
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