ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 15

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Data Arithmetic Unit (DAU)
The data arithmetic unit (DAU) contains a 16 x 16-bit
parallel multiplier that generates a full 32-bit product in
one instruction cycle. The product can be accumulated
with one of two 36-bit accumulators. The accumulator
data can be directly loaded from, or stored to, memory
in two 16-bit words with optional saturation on overflow.
The arithmetic logic unit (ALU) supports a full set of
arithmetic and logical operations on either 16- or 32-bit
data. A standard set of flags can be tested for condition-
al ALU operations, branches, and subroutine calls. This
procedure allows the processor to perform as a power-
ful 16- or 32-bit microprocessor for logical and control
applications. The available instruction set is compatible
with the DSP1618 instruction set. See Section 5.1 for
more information on the instruction set.
The user also has access to two additional DAU regis-
ters. The psw register contains status information from
the DAU (see Table 30, Processor Status Word Regis-
ter). The arithmetic control register, auc, is used to con-
figure some of the features of the DAU (see Table 31)
including single-cycle squaring. The auc register align-
ment field supports an arithmetic shift left by one and
left or right by two. The auc register is cleared by reset.
The counters c0 to c2 are signed, 8 bits wide, and may
be used to count events such as the number of times
the program has executed a sequence of code. They
are controlled by the conditional instructions and pro-
vide a convenient method of program looping.
Y Space Address Arithmetic Unit (YAAU)
The YAAU supports high-speed, register-indirect, com-
pound, and direct addressing of data (Y) memory. Four
general-purpose, 16-bit registers, r0 to r3, are available
in the YAAU. These registers can be used to supply the
read or write addresses for Y space data. The YAAU
also decodes the 16-bit data memory address and out-
puts individual memory enables for the data access.
The YAAU can address the six 1 Kword banks of on-
chip DPRAM or three external data memory segments.
Up to 48 Kwords of off-chip RAM are addressable, with
16K addresses reserved for internal RAM.
Two 16-bit registers, rb and re, allow zero-overhead
modulo addressing of data for efficient filter implemen-
tations. Two 16-bit signed registers, j and k, are used to
hold user-defined postmodification increments. Fixed
increments of +1, –1, and +2 are also available. Four
compound-addressing modes are provided to make
read/write operations more efficient.
Lucent Technologies Inc.
(continued)
The YAAU allows direct (or indexed) addressing of data
memory. In direct addressing, the 16-bit base register
(ybase) supplies the 11 most significant bits of the ad-
dress. The direct data instruction supplies the remaining
5 bits to form an address to Y memory space and also
specifies one of 16 registers for the source or destina-
tion.
X Space Address Arithmetic Unit (XAAU)
The XAAU supports high-speed, register-indirect, in-
struction/coefficient memory addressing with postmodi-
fication of the register. The 16-bit pt register is used for
addressing coefficients. The signed register i holds a
user-defined postincrement. A fixed postincrement of
+1 is also available. Register PC is the program
counter. Registers pr and pi hold the return address for
subroutine calls and interrupts, respectively.
The XAAU decodes the 16-bit instruction/coefficient ad-
dress and produces enable signals for the appropriate
X memory segment. The addressable X segments are
48 Kwords of internal ROM, up to 16 Kwords of DPRAM
for the DSP1628x16 or up to 8 Kwords of DPRAM for
the DSP1628x08, and external ROM.
The locations of these memory segments depend upon
the memory map selected (see Table 5). A security
mode can be selected by mask option. This prevents
unauthorized access to the contents of on-chip ROM
(see Section 7, Mask-Programmable Options).
4.3 Interrupts and Trap
The DSP1628 supports prioritized, vectored interrupts
and a trap. The device has eight internal hardware
sources of program interrupt and two external interrupt
pins. Additionally, there is a trap pin and a trap signal
from the hardware development system (HDS). A soft-
ware interrupt is available through the icall instruction.
The icall instruction is reserved for use by the HDS.
Each of these sources of interrupt and trap has a unique
vector address and priority assigned to it. DSP16A in-
terrupt compatibility is not maintained.
The software interrupt and the traps are always enabled
and do not have a corresponding bit in the ins register.
Other vectored interrupts are enabled in the inc register
(see Table 33, Interrupt Control (inc) Register) and
monitored in the ins register (see Table 34, Interrupt
Status (ins) Register). When the DSP1628 goes into an
interrupt or trap service routine, the IACK pin is assert-
ed. In addition, pins VEC[3:0] encode which interrupt/
trap is being serviced. Table 4 details the encoding
used for VEC[3:0].
DSP1628 Digital Signal Processor
13