ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 74

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

DSP1628 Digital Signal Processor
6 Signal Descriptions
Figure 12 shows the pinout for the DSP1628. The sig-
nals can be separated into five interfaces as shown.
These interfaces and the signals that comprise them
are described below.
6.1 System Interface
The system interface consists of the clock, interrupt,
and reset signals for the processor.
RSTB
Reset: Negative assertion. A high-to-low transition
causes the processor to enter the reset state. The auc,
powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, tim-
erc, timer0, sbit (upper byte), inc, ins (except OBE,
OBE2, and PODS status bits set), alf (upper 2 bits,
AWAIT and LOWPR), ioc, rb, and re registers are
cleared. The mwait register is initialized to all 0s (zero
wait-states) unless the EXM pin is high and the INT1 pin
is low. In that case, the mwait register is initialized to all
1s (15 wait-states).
72
INTERFACE #1
INTERFACE
EXTERNAL
MEMORY
SERIAL
ERAMLO
ERAMHI
DB[15:0]
AB[15:0]
DOEN1
SYNC1
SADD1
EROM
OCK1
DSEL
OLD1
OBE1
RWN
EXM
ICK1
ILD1
IBF1
DO1
DI1
IO
Figure 12. DSP1628 Pinout by Interface
16
16
DSP1628
Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2.
The DAU condition flags are not affected by reset.
IOBIT[7:0] are initialized as inputs. If any of the IOBIT
pins are switched to outputs (by writing sbit), their initial
value will be logic zero (see Figure 44, Register Settings
After Reset).
Upon negation of the signal, the processor begins exe-
cution at location 0x0000 in the active memory map
(see Section 4.4, Memory Maps and Wait-States).
CKI
Input Clock: A mask-programmable option selects one
of three possible input buffers for the CKI pin (see Sec-
tion 7, Mask-Programmable Options, and Table 1, Pin
Descriptions). The internal CKI from the output of the
selected input buffer can then drive the internal proces-
sor clock directly (1X) or drive the on-chip PLL (see
Section 4.13). The PLL allows the CKI input clock to be
at a lower frequency than the internal processor clock.
2
4
4
TRST
TDI
TDO
TCK
TMS
RSTB
CKO
CKI2
CKI
STOP
INT[1:0]
VEC[3:0] OR IOBIT[4:7]
IACK
TRAP
PSTAT OR DO2
PODS OR OLD2
PCSN OR OCK2
POBE OR OBE2
PBSEL OR SYNC2
PB0 OR ICK2
PIDS OR ILD2
PB1 OR DI2
PIBF OR IBF2
PB2 OR DOEN2
PB3 OR SADD2
PB[7:4] OR IOBIT[3:O]
Preliminary Data Sheet
Lucent Technologies Inc.
SERIAL INTERFACE #2
AND CONTROL I/O
CONTROL I/O
PARALLEL HOST
INTERFACE
INTERFACE
INTERFACE
JTAG TEST
SYSTEM
INTERFACE
INTERFACE
February 1997
OR
OR
5-4006 (C).h