ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 49

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
5 Software Architecture
A single-cycle squaring function is provided in DSP1628. By setting the X = Y = bit in the auc register, any instruction
that loads the high half of the y register also loads the x register with the same value. A subsequent instruction to
multiply the x register and y register results in the square of the value being placed in the p register. The instruction
a0 = p p = x*y y = *r0++ with the X = Y = bit set to one will read the value pointed to by r0, load it to both x and
y, multiply the previously fetched value of x and y, and transfer the previous product to a0. A table of values pointed
to by r0 can thus be squared in a pipeline with one instruction cycle per each value. Multiply/ALU instructions that
use x = X transfer statements (such as a0 = p p = x*y y = *r0++ x = *pt++) are not recommended for squaring
Table 17. Multiply/ALU Instructions
† The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.
‡ Add cycles for:
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding CLR bit in the auc
Table 18. Replacement Table for Multiply/ALU Instructions
because pt will be incremented even though x is not loaded from the value pointed to by pt. Also, the same conflict
wait occurrences from reading the same bank of internal memory or reading from external memory apply, since the
X space fetch occurs (even though its value is not used).
Lucent Technologies Inc.
aD = p
aD = aS + p
aD = aS – p
aD = p
aD = aS + p
aD = aS – p
aD = y
aD = aS + y
aD = aS – y
aD = aS & y
aD = aS | y
aD = aS ^ y
aS – y
aS & y
aD, aS, aT
1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.
Function Statement
Replace
register is zero. auc is cleared by reset.
X
Y
Z
a0, a1
*pt++, *pt++i
*rM, *rM++, *rM--, rM++j
*rMzp, *rMpz, *rMm2, *rMjk Read/Write compound addressing. rM (M = 0, 1, 2, 3) is used twice.
p = x * y
p = x * y
p = x * y
p = x * y
Value
(continued)
Transfer Statement
y = Y
y = aT
y[l] = Y
aT[l] = Y
x = Y
Y
Y = y[l]
Y = aT[l]
Z:y
Z:y[l]
Z:aT[l]
One of two DAU accumulators.
X memory space location pointed to by pt. pt is postmodified by +1
and i, respectively.
RAM location pointed to by rM (M = 0, 1, 2, 3). rM is postmodified by
0, +1, –1, or j, respectively.
First, postmodified by 0, +1, –1, or j, respectively; and, second, post-
modified by +1, 0, +2, or k, respectively.
x = X
x = X
x = X
†
Cycles (Out/In Cache)
DSP1628 Digital Signal Processor
2/1
2/1
1/1
1/1
1/1
1/1
2/2
2/2
2/2
2/2
2/2
Meaning
‡
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