ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 19

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Table 4. Interrupt Vector Table
A trap has four cycles of latency. At most, two instruc-
tions will execute from the time the trap is received at
the pin to when it gains control. An instruction that is ex-
ecuting when a trap occurs is allowed to complete be-
fore the trap service routine is entered. (Note that the
instruction could be lengthened by wait-states.) During
normal program execution, the pi register contains ei-
ther the address of the next instruction (two-cycle in-
struction executing) or the address following the next
instruction (one-cycle instruction executing). In an inter-
rupt service routine, pi contains the interrupt return ad-
dress. When a trap occurs during an interrupt service
routine, the value of the pi register may be overwritten.
Specifically, it is not possible to return to an interrupt
service routine from a user trap (0x46) service routine.
Continuing program execution when a trap occurs dur-
ing a cache loop is also not possible.
The HDS trap causes circuitry to force the program
memory map to MAP1 (with on-chip ROM starting at ad-
dress 0x0) when the trap is taken. The previous memo-
ry map is restored when the trap service routine exits by
issuing an ireturn. The map is forced to MAP1 because
the HDS code, if present, resides in the on-chip ROM.
Using the Lucent Technologies development tools, the
TRAP pin may be configured to be an output, or an input
vectoring to address 0x3. In a multiprocessor environ-
ment, the TRAP pins of all the DSPs present can be tied
together. During HDS operations, one DSP is selected
by the host software to be the master. The master pro-
cessor's TRAP pin is configured to be an output.
Lucent Technologies Inc.
* Traps due to HDS breakpoints have no effect on VEC[3:0] pins.
No Interrupt
Software Interrupt
INT0
JINT
INT1
TIME
IBF2
OBE2
Reserved
EREADY
EOVF
IBF
OBE
PIBF
POBE
TRAP from HDS
TRAP from User
Source
Vector
0x42
0x10
0x14
0x18
0x1c
0x20
0x24
0x2c
0x30
0x34
0x38
0x46
0x2
0x1
0x4
0x3
—
(continued)
19 = highest
Priority
10
11
12
14
15
16
17
18
—
1
2
3
4
7
8
9
The TRAP pins of the slave processors are configured
as inputs. When the master processor reaches a break-
point, the master's TRAP pin is asserted. The slave pro-
cessors will respond to their TRAP input by beginning to
execute the HDS code.
AWAIT Interrupt (Standby or Sleep Mode)
Setting the AWAIT bit (bit 15) of the alf register
(alf = 0x8000) causes the processor to go into a power-
saving standby or sleep mode. Only the minimum cir-
cuitry on the chip required to process an incoming inter-
rupt remains active. After the AWAIT bit is set, one
additional instruction will be executed before the stand-
by power-saving mode is entered. A PHIF or SIO word
transfer will complete if already in progress. The AWAIT
bit is reset when the first interrupt occurs. The chip then
wakes up and continues executing.
Two nop instructions should be programmed after the
AWAIT bit is set. The first nop (one cycle) will be exe-
cuted before sleeping; the second will be executed after
the interrupt signal awakens the DSP and before the in-
terrupt service routine is executed.
VEC[3:0]
0x0
0x1
0x2
0x8
0x9
0xc
0xd
0xe
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
*
DSP1628 Digital Signal Processor
breakpoint, jtag, or pin
ECCP overflow
ECCP ready
Issued by
SIO2 out
PHIF out
SIO2 in
SIO out
PHIF in
SIO in
jtag in
timer
icall
pin
pin
pin
—
—
17