ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 43

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
Await Bit of the alf Register
Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power-saving
standby mode. Operation of the AWAIT bit is the same as in the DSP1610, DSP1611, DSP1616, DSP1617, and
DSP1618. In this mode, the minimum circuitry required to process an incoming interrupt remains active, and the PLL
remains active if enabled. An interrupt will return the processor to the previous state, and program execution will
continue. The action resulting from setting the AWAIT bit and the action resulting from setting bits in the powerc
register are mostly independent. As long as the processor is receiving a clock, whether slow or fast, the DSP may
be put into standard sleep mode with the AWAIT bit. Once the AWAIT bit is set, the STOP pin can be used to stop
and later restart the processor clock, returning to the standard sleep state. If the processor clock is not running, how-
ever, the AWAIT bit cannot be set.
Power Management Sequencing
There are important considerations for sequencing the power management modes. The small-signal clock input
circuit has a start-up delay which must be taken into account, and the PLL requires a delay to reach lock-in. Also,
the chip may or may not need to be reset following a return from a low-power state.
Devices with a small-signal input clocking option may use the XTLOFF bit in the powerc register to power down the
on-chip oscillator or small-signal circuitry, thereby reducing the power dissipation. When reenabling the oscillator or
the small-signal circuitry, it is important to bear in mind that a start-up interval exists during which time the clocks
are not stable. Two scenarios exist here:
1. Immediate Turn-Off, Turn-On with RSTB: This scenario applies to situations where the target device is not re-
Lucent Technologies Inc.
2. Running from Slow Clock While XTLOFF Active: The second scenario applies to situations where the device
quired to execute any code while the small-signal input circuit is powered down and where restart from a reset
state can be tolerated. In this case, the processor clock derived from either the oscillator or the small-signal input
is running when XTLOFF is asserted. This effectively stops the internal processor clock. When the system choos-
es to reenable the oscillator or small-signal input, a reset of the device will be required. The reset pulse must be
of sufficient duration for the small-signal start-up interval to be satisfied (required for the small-signal input circuit
to reach its dc operating point). A minimum reset pulse of 20 s will be adequate. The falling edge of the reset
signal, RSTB, will asynchronously clear the XTLOFF field, thus reenabling the power to the small-signal circuitry.
The target DSP will then start execution from a reset state, following the rising edge of RSTB.
needs to continue execution of its target code. In this case, the device switches to the slow ring oscillator clock
first, by enabling the SLOWCKI field. Then, if the small-signal input is being used, power down this circuitry by
writing a 1 to the XTLOFF field. Two nops are needed in between the two write operations to the powerc register.
The target device will then continue execution of its code at slow speed, while the small-signal input clock is
turned off. Switching from the slow clock back to the high-speed clock is then accomplished in three user steps.
First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer to a delay to wait for the small-
signal input oscillations to become stable. When the timer counts down to zero, the high-speed clock is selected
by clearing the SLOWCKI field, either in the timer's interrupt service routine or following a timer polling loop. If
PLL operation is desired, then an additional routine is necessary to enable the PLL and wait for it to lock.
(continued)
DSP1628 Digital Signal Processor
41