ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 41

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
4 Hardware Architecture
4.14 Power Management
There are three different control mechanisms for putting
the DSP1628 into low-power modes: the powerc con-
trol register, the STOP pin, and the AWAIT bit in the alf
register. The PLL can also be disabled with the PLLEN
bit of the pllc register for more power saving.
Powerc Control Register Bits
The powerc register has 10 bits that power down vari-
ous portions of the chip and select the clock source:
XTLOFF: Assertion of the XTLOFF bit powers down the
small-signal input circuit, disabling the internal proces-
sor clock. Since the small-signal input circuit takes
many cycles to stabilize, care must be taken with the
turn-on sequence, as described later.
SLOWCKI: Assertion of the SLOWCKI bit selects the
ring oscillator as the clock source for the internal pro-
cessor clock instead of CKI or the PLL. When CKI or the
PLL is selected, the ring oscillator is powered down.
Switching of the clocks is synchronized so that no par-
tial or short clock pulses occur. Two nops should follow
the instruction that sets or clears SLOWCKI.
NOCK: Assertion of the NOCK bit synchronously turns
off the internal processor clock, regardless of whether
its source is provided by CKI, the PLL, or the ring oscil-
lator. The NOCK bit can be cleared by resetting the chip
with the RSTB pin, or asserting the INT0 or INT1 pins.
Two nops should follow the instruction that sets NOCK.
The PLL remains running, if enabled, while NOCK is
set.
INT0EN: This bit allows the INT0 pin to asynchronously
clear the NOCK bit, thereby allowing the device to con-
tinue program execution from where it left off without
any loss of state. No chip reset is required. It is recom-
mended that, when INT0EN is to be used, the INT0
interrupt be disabled in the inc register so that an unin-
tended interrupt does not occur. After the program re-
sumes, the INT0 interrupt in the ins register should be
cleared.
INT1EN: This bit enables the INT1 pin to be used as the
NOCK clear, exactly like INT0EN previously described.
The following control bits power down the peripheral
I/O units of the DSP. These bits can be used to further
reduce the power consumption during standard sleep
mode.
Lucent Technologies Inc.
(continued)
SIO1DIS: This is a powerdown signal to the SIO1 I/O
unit. It disables the clock input to the unit, thus elimi-
nating any sleep power associated with the SIO1.
Since the gating of the clocks may result in incomplete
transactions, it is recommended that this option be
used in applications where the SIO1 is not used or
when reset may be used to reenable the SIO1 unit.
Otherwise, the first transaction after reenabling the unit
may be corrupted.
SIO2DIS: This bit powers down the SIO2 in the same
way SIO1DIS powers down the SIO1.
PHIFDIS: This is a powerdown signal to the parallel
host interface. It disables the clock input to the unit,
thus eliminating any sleep power associated with the
PHIF. Since the gating of the clocks may result in in-
complete transactions, it is recommended that this op-
tion be used in applications where the PHIF is not
used, or when reset may be used to reenable the
PHIF. Otherwise, the first transaction after reenabling
the unit may be corrupted.
TIMERDIS: This is a timer disable signal which dis-
ables the clock input to the timer unit. Its function is
identical to the DISABLE field of the timerc control
register. Writing a 0 to the TIMERDIS field will continue
the timer operation.
Figure 11 shows a functional view of the effect of the
bits of the powerc register on the clock circuitry. It
shows only the high-level operation of each bit. Not
shown are the bits that power down the peripheral
units.
STOP Pin
Assertion (active-low) of the STOP pin has the same
effect as setting the NOCK bit in the powerc register.
The internal processor clock is synchronously disabled
until the STOP pin is returned high. Once the STOP
pin is returned high, program execution will continue
from where it left off without any loss of state. No chip
reset is required. The PLL remains running, if enabled,
during STOP assertion.
The pllc Register Bits
The PLLEN bit of the pllc register can be used to pow-
er down the clock synthesizer circuitry. Before shutting
down the clock synthesizer circuitry, the system clock
should be switched to either CKI using the PLLSEL bit
of pllc, or to the ring oscillator using the SLOWCKI bit
of powerc.
DSP1628 Digital Signal Processor
39