ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 110

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
10 Timing Characteristics for 2.7 V Operation
10.10 Multiprocessor Communication
* Negative edge initiates time slot 0.
Note: All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive
Table 104. Timing Requirements for SIO Multiprocessor Communication
Table 105. Timing Characteristics for SIO Multiprocessor Communication
* With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.
Lucent Technologies Inc.
OCK/ICK
Abbreviated Reference
Abbreviated Reference
DO/D1
DOEN
SYNC
SADD
multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.
V
V
V
V
V
V
OH
OH
t112
t113
t114
t115
t116
t117
t120
t121
t122
OL
OL
IH
IL
–
–
–
–
–
–
t113
t112
*
Figure 34. SIO Multiprocessor Timing Diagram
B15
*
Sync Setup (high/low to high)
Sync Hold (high to high/low)
Address Setup (valid to high)
Address Hold (high to invalid)
Data Delay (bit 0 only) (low to valid)
Data Disable Delay (high to 3-state)
DOEN Valid Delay (high to valid)
Address Delay (bit 0 only) (low to valid)
Address Disable Delay (high to 3-state)
t112
t113
t120
Parameter
Parameter
AD0
B0
t116
t121
AD1
B1
TIME SLOT 1
AD7
(continued)
B7
AS0
B8
DSP1628 Digital Signal Processor
t122
t120
B15
AS7
Min
Min
35
12
—
—
—
—
—
0
0
t117
Max
Max
t114
AD0
35
30
25
35
30
—
—
—
—
TIME SLOT 2
B0
t115
5-4799 (F)
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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