ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 65

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

February 1997
5 Software Architecture
Table 42. ioc Register*
* The field definitions for the ioc register are different from the DSP1610.
ioc Fields
1. The phase of CKI is synchronized by the rising edge of RSTB.
2. When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator.
3. The wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see Table 40).
4. The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based
Lucent Technologies Inc.
Field Reserved EXTROM CKO2 EBIOH
Bit
During sequenced external memory accesses, it completes one cycle.
on the mwait register setting (see Table 40).
EXTROM
CKO[1:0]
CKO2
ioc Field
WEROM
SIOLBC
DENB3
DENB2
DENB1
DENB0
EBIOH
ESIO2
CKO2
—
0
0
0
0
1
1
1
1
15
CKO1
If 1, sets AB15 low during external memory accesses when WEROM = 1.
CKO configuration (see below).
If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.
If 1, allows writing into external program (X) memory.
If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.
If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO configuration (see below).
If 1, delay EROM.
If 1, delay ERAMHI.
If 1, delay IO.
If 1, delay ERAMLO.
—
0
0
1
1
0
0
1
1
14
CKO0
—
0
1
0
1
0
1
0
1
13
(continued)
CKI/(1 + W)
CKI/(1 + W)
CKI
CKI
1X
1
0
12
CKO Output
Description
WEROM
CKI x (M/(2N)) / [1 + W] Wait-stated clock.
CKI x (M/(2N)) / [1 + W] Sequenced, wait-stated clock.
11
CKI x M/(2N)
Reserved
Reserved
PLL
CKI
ESIO2
1
0
10
SIOLBC
DSP1628 Digital Signal Processor
9
Free-running clock.
Held high.
Held low.
Output of CKI buffer.
CKO[1:0] Reserved DENB[3:0]
8—7
Description
1—3
—
1, 2
6—4
1—4
3—0
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