ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 62

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ds96-039wdsp

Manufacturer Part Number
ds96-039wdsp
Description
Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
Manufacturer
ETC-unknow
Datasheet
DSP1628 Digital Signal Processor
5 Software Architecture
Table 35. timerc Register
PRESCALE Field
Table 36. Phase-Locked Loop Control (pllc) Register
60
Field
PRESCALE
Bit
Field
DISABLE
PRESCALE
RELOAD
Reserved
Mbits[4:0]
Bit
Nbits[2:0]
PLLSEL
T0EN
Field
PLLEN
LF[3:0]
Field
0000
0001
0010
0011
0100
0101
0110
0111
ICP
Reserved
PLLEN
15—7
15
Value
Value
0
1
0
1
0
1
0
1
0
1
0
Timer Interrupts
Frequency of
PLLSEL
CKO/128
CKO/256
Timer enabled.
Timer and prescaler disabled. The period register and timer0 are
not reset.
Timer stops after counting down to 0.
Timer automatically reloads and repeats indefinitely.
Timer holds current count.
Timer counts down to 0.
See table below.
CKO/16
CKO/32
CKO/64
CKO/2
CKO/4
CKO/8
14
PLL powered down.
PLL powered up.
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
Charge pump current selection (see Table 64 for proper value).
Loop filter setting (see Table 64 for proper value).
Encodes N, 1 N 8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1.
Encodes M, 2
DISABLE
(continued)
6
ICP
13
M
RELOAD
20, where M = Mbits[4:0] + 2, f
5
Reserved
PRESCALE
Description
12
1000
1001
1010
1011
1100
1101
1110
1111
T0EN
Description
4
LF[3:0]
11—8
Timer Interrupts
Frequency of
CKO/16384
CKO/32768
CKO/65536
CKO/1024
CKO/2048
CKO/4096
CKO/8192
CKO/512
PRESCALE
3—0
INTERNAL CLOCK
Nbits[2:0]
7—5
Lucent Technologies Inc.
= f
February 1997
CKI
Mbits[4:0]
x (M/(2N)).
4—0

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