ds96-039wdsp ETC-unknow, ds96-039wdsp Datasheet - Page 4

• Manufacturer Part Number: ds96-039wdsp
• Description: Clarification Serial Control Register Description Dsp1620/27/28/29 Devices
• Manufacturer: ETC-unknow

Contents
1 Features ...................................................................1
2 Description ...............................................................1
3 Pin Information .........................................................3
4 Hardware Architecture..............................................8
5 Software Architecture .............................................46
6 Signal Descriptions.................................................72
7 Mask-Programmable Options.................................78
8 Device Characteristics............................................79
9 Electrical Characteristics and Requirements..........81
DSP1628 Digital Signal Processor
2
4.1 DSP1628 Architectural Overview.......................8
4.2 DSP1600 Core Architectural Overview ............12
4.3 Interrupts and Trap...........................................13
4.4 Memory Maps and Wait-States........................18
4.5 External Memory Interface (EMI) .....................21
4.6 Bit Manipulation Unit (BMU).............................22
4.7 Serial I/O Units (SIOs)......................................22
4.8 Parallel Host Interface (PHIF) ..........................24
4.9 Bit Input/Output Unit (BIO) ...............................25
4.10 Timer ..............................................................26
4.11 Error Correction Coprocessor (ECCP)...........26
4.12 JTAG Test Port ..............................................34
4.13 Clock Synthesis..............................................36
4.14 Power Management .......................................39
5.1 Instruction Set ..................................................46
5.2 Register Settings..............................................55
5.3 Instruction Set Formats ....................................66
6.1 System Interface ..............................................72
6.2 External Memory Interface ...............................74
6.3 Serial Interface #1 ............................................75
6.4 Parallel Host Interface or Serial
6.5 Control I/O Interface.........................................76
6.6 JTAG Test Interface .........................................77
7.1 Input Clock Options..........................................78
7.2 Memory Map Options.......................................78
7.3 ROM Security Options .....................................78
8.1 Absolute Maximum Ratings .............................79
8.2 Handling Precautions .......................................79
8.3 Recommended Operating Conditions ..............79
8.4 Package Thermal Considerations ....................80
9.1 Power Dissipation ............................................84
Interface #2 and Control I/O Interface..............76
Table of Contents
Page
Contents
10 Timing Characteristics for 2.7 V Operation........... 86
11 Outline Diagrams................................................ 109
10.1 DSP Clock Generation ................................... 87
10.2 Reset Circuit...................................................88
10.3 Reset Synchronization ................................... 89
10.4 JTAG I/O Specifications ................................. 90
10.5 Interrupt .......................................................... 91
10.6 Bit Input/Output (BIO)..................................... 92
10.7 External Memory Interface ............................. 93
10.8 PHIF Specifications ........................................ 97
10.9 Serial I/O Specifications ............................... 103
10.10 Multiprocessor Communication .................. 108
11.1 100-Pin BQFP (Bumpered Quad
11.2 100-Pin TQFP (Thin Quad Flat Pack) .......... 110
11.3 144-Pin PBGA (Plastic Ball Grid Array)........ 111
Flat Pack) .................................................... 109
Lucent Technologies Inc.
February 1997
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