mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 138

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Operation
4.9.1.1 Cacheable Accesses
If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the
access is cacheable. A read access to a write-through or copyback region is read from the
cache if matching data is found. Otherwise, the data is read from memory and the cache is
updated. When a line is being read from memory for either a write-through or copyback
read miss, the longword within the line that contains the core-requested data is loaded first
and the requested data is given immediately to the processor, without waiting for the three
remaining longwords to reach the cache.
The following sections describe write-through and copyback modes in detail. Note that
some of this information applies to data caches only.
4.9.1.2 Write-Through Mode (Data Cache Only)
Write accesses to regions specified as write-through are always passed on to the external
bus, although the cycle can be buffered, depending on the state of CACR[DESB]. Writes in
write-through mode are handled with a no-write-allocate policy—that is, writes that miss
in the cache are written to the external bus but do not cause the corresponding line in
memory to be loaded into the cache. Write accesses that hit always write through to
memory and update matching cache lines. The cache supplies data to data-read accesses
that hit in the cache; read misses cause a new cache line to be loaded into the cache.
4.9.1.3 Copyback Mode (Data Cache Only)
Copyback regions are typically used for local data structures or stacks to minimize external
bus use and reduce write-access latency. Write accesses to regions specified as copyback
that hit in the cache update the cache line and set the corresponding M bit without an
external bus access.
Be sure to flush the cache using the CPUSHL instruction before invalidating the cache in
copyback mode. Modified cache data is written to memory only if the line is replaced
because of a miss or a CPUSHL instruction pushes the line. If a byte, word, longword, or
line write access misses in the cache, the required cache line is read from memory, thereby
updating the cache. When a miss selects a modified cache line for replacement, the
modified cache data moves to the push buffer. The replacement line is read into the cache
and the push buffer contents are then written to memory.
4.9.2 Cache-Inhibited Accesses
Memory regions can be designated as cache-inhibited, which is useful for memory
containing targets such as I/O devices and shared data structures in multiprocessing
systems. It is also important to not cache the MCF5407 memory mapped registers. If the
corresponding ACRn[CM] or CACR[DDCM] indicates cache-inhibited, precise or
imprecise, the access is cache-inhibited. The caching operation is identical for both
cache-inhibited modes, which differ only regarding recovery from an external bus error.
MCF5407 User’s Manual
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