mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 152

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Operation Summary
4.12.2 Data Cache State Transitions
Using the V and M bits, the data cache supports a line-based protocol allowing individual
cache lines to be invalid, valid, or modified. To maintain memory coherency, the data cache
supports both write-through and copyback modes, specified by the corresponding
ACR[CM], or CACR[DDCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line
from memory into the cache. If available, tag and data from memory update an invalid line
in the selected set. The line state then changes from invalid to valid by setting the V bit. If
all lines in the row are already valid or modified, the pseudo-round-robin replacement
algorithm selects one of the four lines and replaces the tag and data. Before replacement,
modified lines are temporarily buffered and later copied back to memory after the new line
has been read from memory.
Figure 4-13 shows the three possible data cache line states and possible processor-initiated
transitions for memory configured as copyback. Transitions are labeled with a capital letter
indicating the previous state and a number indicating the specific case listed in Table 4-7.
4-28
Cache
invalidate
Cache
push
Access
CI5—DCINVA
CI6—CPUSHL & DDPI
CI7—CPUSHL & DDPI
Table 4-6. Instruction Cache Line State Transitions (Continued)
II5 No action;
II6,
II7
Figure 4-13. Data Cache Line State Diagram—Copyback Mode
stay in invalid state.
No action;
stay in invalid state.
CD5—DCINVA
CD6—CPUSHL & DDPI
Invalid
Invalid (V = 0)
V = 0
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
CI3—CPU
write miss
MCF5407 User’s Manual
CI1—CPU read miss
CV5—DCINVA
CV6—CPUSHL & DDPI
CD7—CPUSHL
& DDPI
Modified
M = 1
V = 1
Current State
CD1—CPU
read miss
IV5 No action;
IV6 No action;
IV7 No action;
go to invalid state.
go to invalid state.
stay in valid state.
CV3—CPU write miss
CV4—CPU write hit
Valid (V = 1)
M = 0
V = 1
Valid
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DDPI