mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 300

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mcf5407

Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Synchronous Operation
11.4.4.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at
the same time to perform an internal refresh operation and to maintain the integrity of the
data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS].
When IS is set, the
command is sent to the DRAM controller. Figure 11-23 shows the self-refresh operation.
11.4.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller
(DCR[COC] = 0)
11-32
RAS[0] or [1]
RAS[0] or [1]
DRAMW
A[31:0]
DRAMW
CLKIN
SRAS
SCAS
CLKIN
SRAS
SCAS
SCKE
PALL
PALL
SELF
t
t
RCD
NOP
RCD
NOP
= 2
Figure 11-22. Auto-Refresh Operation
= 2
Figure 11-23. Self-Refresh Operation
command is sent to the SDRAM. When IS is cleared, the
SELF
REF
Refresh
MCF5407 User’s Manual
Active
Self-
SELFX
t
RC
NOP
t
RC
= 6
= 6
NOP
Possible
ACTV
ACTV
First
SELFX

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