mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 25

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Figure
Number
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
14-21
14-22
14-24
14-23
14-25
14-26
14-27
14-28
14-29
14-30
14-31
14-32
14-33
14-34
14-35
14-36
14-37
14-38
14-39
15-1
15-2
15-3
16-1
16-2
16-3
17-1
17-2
Modem Control Register (MODCTL) ........................................................................ 14-9
Tx FIFO Threshold Register (TXLVL) .................................................................... 14-10
UART Status Register (USRn) ................................................................................. 14-10
UART Clock-Select Register (UCSRn).................................................................... 14-12
Receive Samples Available Register (RSMP).......................................................... 14-13
Tx Space Available Register (TSPC) ....................................................................... 14-13
UART Command Register (UCRn).......................................................................... 14-14
UART Receiver Buffer for UART0 (URB0)............................................................ 14-16
UART Receiver Buffer for UART1 (URB1)............................................................ 14-16
UART Transmitter Buffer for UART0 (UTB0) ....................................................... 14-16
UART Transmitter Buffer for UART1 (UTB1) ....................................................... 14-17
UART Input Port Change Register (UIPCRn).......................................................... 14-17
UART Auxiliary Control Register (UACRn) ........................................................... 14-18
UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-18
UART Divider Upper Register (UDUn)................................................................... 14-19
UART Divider Lower Register (UDLn)................................................................... 14-19
UART Interrupt Vector Register (UIVRn) ............................................................... 14-20
UART Input Port Register (UIPn) ............................................................................ 14-20
UART Block Diagram Showing External and Internal Interface Signals ................ 14-21
UART Output Port Data 1 Register (UOP1/UOP0) ................................................. 14-21
UART/RS-232 Interface ........................................................................................... 14-23
UART1/CODEC Interface........................................................................................ 14-23
UART1/AC ’97 Interface ......................................................................................... 14-23
Clocking Source Diagram......................................................................................... 14-24
Transmitter and Receiver Functional Diagram......................................................... 14-25
Transmitter Timing Diagram .................................................................................... 14-27
16-Bit CODEC Interface Timing (lsb First) ............................................................. 14-27
8-Bit CODEC Interface Timing (msb First) ............................................................. 14-28
AC ‘97 Interface Timing........................................................................................... 14-28
Receiver Timing........................................................................................................ 14-30
Automatic Echo ........................................................................................................ 14-34
Local Loop-Back ...................................................................................................... 14-34
Remote Loop-Back ................................................................................................... 14-35
Multidrop Mode Timing Diagram ............................................................................ 14-36
UART Mode Programming Flowchart ..................................................................... 14-39
Parallel Port Pin Assignment Register (PAR) ............................................................ 15-1
Port A Data Direction Register (PADDR).................................................................. 15-2
Port A Data Register (PADAT) .................................................................................. 15-3
Mechanical Diagram................................................................................................... 16-9
MCF5407 Case Drawing (General View) ................................................................ 16-10
Case Drawing (Details)............................................................................................. 16-11
MCF5407 Block Diagram with Signal Interfaces ...................................................... 17-2
MCF5307 to MCF5407 TM[2:0] Pin Remapping .................................................... 17-18
ILLUSTRATIONS
Illustrations
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