mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 279

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

11.3.3.1 Non-Page-Mode Operation
In non-page mode, the simplest mode, the DRAM controller provides termination and runs
a separate bus cycle for each data transfer. Figure 11-5 shows a non-page-mode access in
which a DRAM read is followed by a write. Addresses for a new bus cycle are driven at the
rising clock edge.
For a DRAM block hit, the associated RAS is driven at the next falling edge. Here
DACRn[RCD] = 0, so the address is multiplexed at the next rising edge to provide the
column address. The required CAS signals are then driven at the next falling edge and
remain asserted for the period programmed in DACRn[CAS]. Here, DACRn[RNCN] = 1,
so it is precharged one clock before CAS is negated. On a read, data is sampled on the last
rising edge of the clock that CAS is valid.
RAS[1] or [0]
MCF5407 Address
Figure 11-5. Basic Non-Page-Mode Operation RCD = 0, RNCN = 1 (4-4-4-4)
CAS[3:0]
DRAMW
D[31:0]
A[31:0]
CLKIN
Pin
15
14
13
12
11
10
17
19
21
23
25
9
Table 11-9. DRAM Addressing for 32-Bit Wide Memories
Row
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
MCF5407 Address Bit
DACRn[RCD] = 0
Driven for RAS
15
14
13
12
11
10
17
19
21
23
25
9
DACRn[CAS] = 01]
Column
DACRn[RNCN] = 1
MCF5407 Address Bit Driven
when CAS is Asserted
16
18
20
22
24
2
3
4
5
6
7
8
Asynchronous Operation
Base Memory Size of
Memory Size
256 Kbytes
16 Mbytes
64 Mbytes
64 Kbytes
4 Mbytes
1 Mbyte
11-11