mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 16
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mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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Paragraph
Number
17.2.1.1
17.2.1.2
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.2.7
17.2.8
17.2.9
17.2.10
17.3
17.3.1
17.4
17.4.1
17.4.2
17.4.3
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.5.5.1
17.5.5.2
17.5.5.3
17.5.5.4
17.5.6
17.5.6.1
17.6
17.6.1
17.6.2
17.6.3
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
17.7.7
17.8
17.8.1
xvi
Interrupt Control Signals................................................................................. 17-12
Bus Arbitration Signals................................................................................... 17-12
Clock and Reset Signals.................................................................................. 17-13
Chip-Select Module Signals ........................................................................... 17-15
DRAM Controller Signals .............................................................................. 17-16
DMA Controller Module Signals.................................................................... 17-17
Data Bus (D[31:0]) ....................................................................................... 17-8
Read/Write (R/W)......................................................................................... 17-8
Size (SIZ[1:0]) .............................................................................................. 17-8
Transfer Start (TS) ........................................................................................ 17-9
Address Strobe (AS) ..................................................................................... 17-9
Transfer Acknowledge (TA) ......................................................................... 17-9
Transfer In Progress (TIP/PP7)................................................................... 17-10
Transfer Type (TT[1:0]/PP[1:0]) ................................................................ 17-10
Transfer Modifier (TM[2:0]/PP[4:2]/DACK[1:0])..................................... 17-10
Interrupt Request (IRQ1/IRQ2, IRQ3/IRQ6, IRQ5/IRQ4, and IRQ7)....... 17-12
Bus Request (BR) ....................................................................................... 17-12
Bus Driven (BD)......................................................................................... 17-13
Reset In (RSTI)........................................................................................... 17-13
Clock Input (CLKIN).................................................................................. 17-13
Bus Clock Output (BCLKO) ...................................................................... 17-13
Reset Out (RSTO)....................................................................................... 17-13
Data/Configuration Pins (D[7:0]) ............................................................... 17-14
D4—Address Configuration (ADDR_CONFIG) ....................................... 17-15
Chip-Select (CS[7:0]) ................................................................................. 17-15
Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16
Output Enable (OE) .................................................................................... 17-16
Row Address Strobes (RAS[1:0])............................................................... 17-16
Column Address Strobes (CAS[3:0]) ......................................................... 17-16
DRAM Write (DRAMW)........................................................................... 17-16
Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17
Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17
Synchronous DRAM Clock Enable (SCKE) .............................................. 17-17
Synchronous Edge Select (EDGESEL) ...................................................... 17-17
DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-17
Bus Grant (BG).......................................................................................... 17-12
Address Bus (A[23:0]).............................................................................. 17-7
Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7
D[7:5,3]—Boot Chip-Select (CS0) Configuration ................................. 17-14
D7—Auto Acknowledge Configuration (AA_CONFIG) ...................... 17-14
D[6:5]—Port Size Configuration (PS_CONFIG[1:0]) ........................... 17-14
D3—Byte-Enable Configuration (BE_CONFIG) .................................. 17-15
D[2:0]—Divide Control (DIVIDE[2:0]) ................................................ 17-15
MCF5407 User’s Manual
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