mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 320

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Address
DMA Controller Module Programming Model
DSR[DONE], shown in Figure 12-9, is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set
and no transfer occurs. See Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
12.4.4 DMA Control Registers (DCR0–DCR3)
DCRn, Figure 12-8, is used for configuring the DMA controller module.
Table 12-4 describes DCR fields.
31
30
12-8
Address
Bits
Reset
Reset
Reset
Field INT EEXT
Field
R/W
R/W
Field
R/W
INT
EEXT
Name
31
AT
31
15
0
30
14
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a
transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the START
bit and DREQ when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. Internal request is always enabled. It is initiated by
writing a 1 to the START bit.
—
—
CS
29
Figure 12-8. DMA Control Registers (DCRn)
Figure 12-7. Byte Count Registers (BCRn)
AA
28
Table 12-4. DCRn Field Descriptions
24 23
27
BWC
MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
MBAR + 0x308, 0x348, 0x388, 0x3A8
MCF5407 User’s Manual
25
0000_0000_0000_0000
SAA S_RW SINC
24
0000_0000_0000_0000_0000_0000
R/W
R/W
R/W
Description
23
N/A
—
22
BCR
21
SSIZE
20
DINC
19
18
DSIZE
17
START
16
0
0