mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 474

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Restrictions
19.4.4 JTAG Bypass Register
The IEEE Standard 1149.1-compliant bypass register creates a single-bit shift register path
from TDI to the bypass register to TDO when the BYPASS instruction is selected.
19.5 Restrictions
Test logic design is static, so TCK can be stopped in high or low state with no data loss.
However, system logic uses a different system clock not internally synchronized to TCK.
Operation mixing 1149.1 test logic with system functional logic that uses both clocks must
coordinate and synchronize these clocks externally to the MCF5407.
19.6 Disabling IEEE Standard 1149.1 Operation
There are two ways to use the MCF5407 without IEEE Standard 1149.1 test logic being
active:
19-10
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Bit
Cell Type
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
D26
D26
D27
D27
D28
D28
D29
D29
D30
D30
D31
D31
SDA
SDA
SCL
SCL
BE3
BE2
BE1
Pin Cell
Table 19-4. Boundary-Scan Bit Definitions
Pin Type
MCF5407 User’s Manual
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
Bit
Cell Type
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
O.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
Pin Cell
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O