mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 76

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
2.2.1.6 MAC Programming Model
Figure 2-3 shows the registers in the MAC portion of the user programming model. These
registers are described as follows:
2.2.2 Supervisor Programming Model
The MCF5407 supervisor programming model is shown in Figure 2-3. Typically, system
programmers use the supervisor programming model to implement operating system
functions and provide memory and I/O control. The supervisor programming model
provides access to the user registers and additional supervisor registers, which include the
upper byte of the status register (SR), the vector base register (VBR), and registers for
configuring attributes of the address space connected to the Version 4 processor core. Most
supervisor-level registers are accessed by using the MOVEC instruction with the control
register definitions in Table 2-2.
2-10
Bits
7–5
4
3
2
1
0
• Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to
• Mask register (MASK)—This 16-bit general-purpose register provides an optional
• MAC status register (MACSR)—This 8-bit register defines configuration of the
Name
accumulate the results of MAC operations.
address mask for MAC instructions that fetch operands from memory. It is useful in
the implementation of circular queues in operand memory.
MAC unit and contains indicator flags affected by MAC instructions. Unless noted
otherwise, MACSR indicator flag settings are based on the final result, that is, the
result of the final operation involving the product and accumulator.
—
X
N
V
C
Z
Reserved, should be cleared.
Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not
affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic.
Negative condition code bit. Set if the msb of the result is set; otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be
represented in the operand size; otherwise cleared.
Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a
borrow occurs in a subtraction; otherwise cleared.
Table 2-1. CCR Field Descriptions
MCF5407 User’s Manual
Description