mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 36

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Organization
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• Part II, “System Integration Module (SIM),” describes the system integration
— Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the
— Chapter 4, “Local Memory.” This chapter describes the MCF5407
— Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug
module, which provides overall control of the bus and serves as the interface
between the ColdFire core processor complex and internal peripheral devices. It
includes a general description of the SIM and individual chapters that describe
components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt
controller for peripherals, configuration and operation of chip selects, and the
SDRAM controller.
— Chapter 6, “SIM Overview,” describes the SIM programming model, bus
— Chapter 7, “Phase-Locked Loop (PLL),” describes configuration and operation
— Chapter 8, “I2C Module,” describes the MCF5407 I
— Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller
— Chapter 10, “Chip-Select Module,” describes the MCF5407 chip-select
— Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
MCF5407 multiply/accumulate unit, which executes integer multiply,
multiply-accumulate, and miscellaneous register instructions. The MAC is
integrated into the operand execution pipeline (OEP).
implementation of the ColdFire V4 local memory specification. It consists of the
two following major sections.
– Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM
– Section 4.7, “Cache Overview,” describes the MCF5407 cache
support in the MCF5407. This revision of the ColdFire debug architecture
encompasses earlier revisions.
arbitration, and system-protection functions for the MCF5407.
of the PLL module. It describes in detail the registers and signals that support the
PLL implementation.
protocol, clock synchronization, and the registers in the I
It also provides extensive programming examples.
portion of the SIM. Includes descriptions of the registers in the interrupt
controller memory map and the interrupt priority scheme.
implementation, including the operation and programming model, which
includes the chip-select address, mask, and control registers.
describes configuration and operation of the synchronous/asynchronous DRAM
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interacts with other memory
structures.
MCF5407 User’s Manual
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C module, including I
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C programing model.
2
C