mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 150

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Management
The following CACR loads assume the instruction cache has been invalidated, the default
instruction cache mode is cacheable, and the default data cache mode is copyback.
dataCacheLoadAndLock:
The following code preloads half of the data cache (4 Kbytes). It assumes a contiguous
block of data is to be mapped into the data cache, starting at a 0-modulo-4K address.
dataCacheLoop:
; A 4K region has been loaded into levels 0 and 1 of the 8K data cache. lock it!
The following CACR loads assume the data cache has been invalidated, the default
instruction cache mode is cacheable and the default operand cache mode is copyback.
Note that this function must be mapped into a cache inhibited or SRAM space or these text
lines will be prefetched into the instruction cache, which may displace some of the 8-Kbyte
space being explicitly fetched.
instructionCacheLoadAndLock:
The following code segments preload half of the instruction cache (8 Kbytes). It assumes a
contiguous block of data is to be mapped, starting at a 0-modulo-8K address
instCacheLoop:
;
; Note in the assembler we use, there is no INTOUCH opcode. The following
; is used to produce the required binary representation
4-26
addq.l
move.l
cmpi.l
bne
rts
move.l
movec
move.l
lea
tst.b
lea
subq.l
bne.b
move.l
movec
rts
align
move.l
movec
move.l #512,d0
lea
intouch (a0)
cpushl
code_,a0
#0xa3080800,d0; enable and invalidate data cache ...
d0,cacr ; ... in the CACR
#256,d0
data_,a0
(a0)
16(a0),a0
#1,d0
dataCacheLoop
#0xaa088000,d0
d0,cacr
16
#0xa2088100,d0
d0,cacr
#nc,(a0)
#1,d0
d0,a0
#4,d0
setloop
MCF5407 User’s Manual
;256 16-byte lines in 4K space
; load pointer defining data area
;touch location + load into data cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
;set the data cache lock bit ...
; ... in the CACR
;enable and invalidate the instruction
;cache in the CACR
;512 16-byte lines in 8K space
;load pointer defining code area
;touch location + load into instruction cache
;touch location + load into
;increment to next way
;set = 0, way = d0
;flushed all the ways?