mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 176

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
A write to the XTDR clears the trigger status bits, CSR[BSTAT].
Section 5.4.9, “Resulting Set of Possible Trigger Combinations,” describes how to handle
multiple breakpoint conditions.
Table 5-18 describes XTDR fields.
29/13
28–22
12–6
28/12
27/11
26/10
25/9
24/8
23/7
22/6
5-20
DRc[4–0]
Bits
Reset
Reset
Field
Field
R/W
R/W
Name
EBL
EDx
31
15
—
—
—
—
—
—
30
14
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR and XTDR (by clearing
TDR[29,13] and XTDR[29,13]) before defining triggers.
Figure 5-14. Extended Trigger Definition Register (XTDR)
Enable breakpoint level. If set, EBL is the global enable for the breakpoint trigger; that is, if
TDR[EBL] or XTDR[EBL] is set, a breakpoint trigger is enabled. Clearing both disables all
breakpoints.
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU Upper data word.
EDLL
EDLM
EDUM
EDUU
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU
29
13
Data longword. Entire processor’s local data bus.
Lower data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
28
12
Table 5-18. XTDR Field Descriptions
27
11
MCF5407 User’s Manual
26
10
25
NOTE:
9
Second-Level Triggers
000_0000_0000_000
000_0000_0000_000
First-Level Triggers
24
8
Description
0x17
Write
Write
23
7
22
6
DI
DI
21
5
EAI
EAI
20
4
EAR
EAR
19
3
EAL
EAL
18
2
17 16
1
—
—
—
—
—
—
0