mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 234

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

PLL Port List
7.3 PLL Port List
Table 7-3 describes PLL module inputs.
Table 7-4 describes PLL module outputs.
7.4 Timing Relationships
The MCF5407 CLKIN frequency can be 1/3, 1/4, 1/5, or 1/6 the processor clock. In this
document, bus timings are referenced from CLKIN.
Regardless of the CLKIN frequency driven at power-up, CLKIN and BCLKO have the
same ratio value to the PCLK. Although either signal can be used as a clock reference,
CLKIN leaves more room to meet the bus specifications than BCLKO, which is generated
as a phase-aligned signal to CLKIN.
Although the CLKIN duty cycle remains the same for the MCF5307 and MCF5407,
caution should be used when interfacing signals on the falling edge of CLKIN with only a
4-nS window to work from at high frequencies. Also, note that the MCF5407 CLKIN rise
time is reduced to 2 nS (5 nS in the MCF5307).
If signals are referenced from CLKIN only, setting PLLCR[DISBCLKO] and disabling
BCLKO reduces power consumption. See Section 7.2.4, “PLL Control Register (PLLCR).”
7.4.1 PCLK, PSTCLK, and BCLKO
Figure 7-3 shows the frequency relationships between PCLK, PSTCLK, and the four
7-4
CLKIN
RSTI
DIVIDE[2:0] TheMCF5407 samples clock ratio encodings on the lower data bits of the bus to determine the
BCLKO
PSTCLK
RSTO
Output
SIgnal
This bus clock output provides a divided version of the processor clock frequency, determined by
DIVIDE[2:0]. BCLKO is provided for MCF5307 compatibility (slower-speed designs).
Provides a buffered processor status clock. PSTCLK is half the frequency of PCLK. See Section 7.4.1,
“PCLK, PSTCLK, and BCLKO,” and Figure 7-1.
This output provides an external reset for peripheral devices.
Input clock to the PLL. Input frequency must not be changed during operation. Changes are
recognized only at reset.
Active-low asynchronous input that, when asserted, indicates PLL is to enter reset mode. As long as
RSTI is asserted, the PLL is held in reset and does not begin to lock.
CLKIN-to-processor clock ratio. D[2:0]/DIVIDE[2:0] support the divide-ratio combinations. Note that
only specific CLKIN ranges are allowed for each divide ratio on the MCF5407. See the electrical
specifications for valid frequencies.
Table 7-4. PLL Module Output Signals
Table 7-3. PLL Module Input SIgnals
MCF5407 User’s Manual
Description
Description