mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 14

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

CAS Latency (CL)
Figure 5:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
CAS Latency
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to one, two or
three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 7 on page 15 indicates the operating
frequencies at which each CL setting can be used.
COMMAND
COMMAND
COMMAND
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
CLK
CLK
CLK
DQ
DQ
DQ
READ
READ
READ
T0
T0
T0
t
t AC
LZ
CL = 1
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
D
t OH
OUT
CL = 3
14
T2
NOP
T2
NOP
T2
t
t AC
LZ
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition