mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 21

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 9:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
CAS Latency
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1. This is shown in Figure 10 on page 22 for CAS latencies
of one, two and three; data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and there-
fore does not require the 2n rule associated with a prefetch architecture.
COMMAND
COMMAND
COMMAND
A READ command can be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be performed to the same bank, as
shown in Figure 11 on page 23, or each subsequent READ may be performed to a
different bank.
CLK
CLK
CLK
DQ
DQ
DQ
READ
READ
READ
T0
T0
T0
t
t AC
LZ
CL = 1
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
D
t OH
OUT
CL = 3
21
T2
NOP
T2
NOP
T2
t
t AC
LZ
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition