mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 53

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 37:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
A0–A9, A11
COMMAND
Self Refresh Mode
BA0, BA1
DQM0–3
Notes:
CLK
CKE
A10
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
1. No maximum time limit for self refresh.
2.
3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
t CKH
t CMH
t
AH
t CK
3b.
3a. The DRAM has been in self refresh mode for a minimum of 64µs prior to exiting.
3c. At least two AUTO REFRESH commands are preformed during each 15.6µs interval while
t
mode until all rows have been refreshed by the AUTO REFRESH command at the distributed
refresh rate,
XSR requires minimum of two clocks regardless of frequency or timing.
t
the DRAM remains out of the self refresh mode.
XSR is not violated.
t RP
T1
NOP
t CH
Enter self refresh mode
t
REF, or faster. However, the following exceptions are allowed:
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
> t RAS
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(Restart refresh time base)
Exit self refresh mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
Tn + 1
RAS(MAX) applies to non-self refresh mode.
t XSR
NOP
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t CKS
To + 1
To + 2
REFRESH
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
AUTO
DON’T CARE
UNDEFINED
Timing Diagrams