mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 60

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mt48lc4m32b2tg-7-it

Manufacturer Part Number
mt48lc4m32b2tg-7-it
Description
128mb X32 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
Figure 44:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
COMMAND
A0–A9, A11
BA0, BA1
DQM0–3
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Write – Without Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. Faster frequencies require two clocks (when
3. A8, A9, and A11 = “Don’t Care.”
4.
t
WR of 1 CLK available if running 100 MHz or slower. Check factory for availability.
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
60
D
IN
T4
NOP
m + 2
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DS
D
IN
T5
NOP
m + 3
t DH
t
WR >
t WR
SINGLE BANK
PRECHARGE
t
2
ALL BANKs
CK).
BANK
T6
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
NOP
t RP
T7
Timing Diagrams
ACTIVE
ROW
ROW
BANK
T8
DON’T CARE
UNDEFINED

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