mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 8

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Table 4:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
2, 4, 5, 7, 8, 10, 11,
3, 9, 35, 41, 49, 55,
13, 74, 76, 77, 79,
80, 82, 83, 85, 31,
33, 34, 36, 37, 39,
40, 42, 45, 47, 48,
14, 30, 57, 69, 70,
25–27, 60–66, 24,
50, 51, 53, 54, 56
6, 12, 32, 38, 46,
Pin Numbers
16, 71, 28, 59
44, 58, 72, 86
1, 15, 29, 43
17, 18, 19
52, 78, 84
22, 23
75, 81
68
67
20
21
73
Pin Descriptions
BA0, BA1
Symbol
DQM0–
A0–A11
DQM3
CAS#,
DQ31
V
DQ0–
WE#,
RAS#
V
CKE
V
CLK
CS#
V
NC
DD
SS
DD
SS
Q
Q
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Type
–
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF REFRESH
operation (all banks idle), active power-down (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH, but
READ/WRITE bursts already in progress will continue and DQM operation will
retain its DQ mask capability while CS# is HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part of the
command code.
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command
being entered.
Input/Output mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (two-
clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1
corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3
corresponds to DQ24–DQ31. DQM0–DQM3 are considered same state when
referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A10) and READ/WRITE command (column-address A0–A7 with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data I/Os: Data bus.
No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL
reference voltage supply.
DQ power supply: Isolated on the die for improved noise immunity.
DQ ground: Provide isolated ground to DQs for improved noise immunity.
Power supply: +3.3V ±0.3V.
Ground.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
Description
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM