mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 27

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

WRITEs
Figure 16:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 17 on page 28). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
A8, A9, A11
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 18 on page 28. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. This 128Mb SDRAM uses a
pipelined architecture and therefore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 19 on page 28, or each subsequent
WRITE may be performed to a different bank.
A0–A7
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
DON’T CARE
27
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©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition