mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 32

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 24:
Clock Suspend
Figure 25:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
Power-Down
CLOCK SUSPEND During WRITE Burst
Notes:
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 22 on page 30 and Figure 23 on page 31.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
COMMAND
1. For this example, BL = 4 or greater, and DM is LOW.
CLK
CKE
INTERNAL
ADDRESS
CLOCK
All banks idle
Enter power-down mode.
CKE
CLK
D
IN
t CKS
NOP
T0
NOP
WRITE
BANK,
COL n
D
T1
n
IN
Input buffers gated off
T2
32
(
(
(
(
)
(
)
)
)
)
(
(
(
(
)
(
)
)
)
)
T3
Exit power-down mode.
NOP
n + 1
T4
D
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IN
> t CKS
DON’T CARE
T5
n + 2
NOP
D
NOP
IN
DON’T CARE
ACTIVE
t RCD
t RAS
t RC
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition