mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 20

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 7:
READs
Figure 8:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
Example: Meeting
READ Command
Notes:
COMMAND
1.
READ bursts are initiated with a READ command, as shown in Figure 8.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 9 on page 21 shows general
timing for each possible CL setting.
A8, A9, A11
t
t
where x = number of clocks for equation to be true.
A0–A7
RCD (MIN) = 20ns,
RCD (MIN) ×
BA0,1
RAS#
CAS#
CLK
WE#
CLK
CKE
A10
CS#
t
RCD (MIN) When 2 <
HIGH
ACTIVE
T0
t
CK
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
t CK
t
CK = 8ns
COLUMN
ADDRESS
ADDRESS
BANK
t
t RCD (MIN) +0.5 t CK
NOP
RCD (MIN)
DON’T CARE
T1
20
t
RCD (MIN)/
t CK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T2
t
CK< 3
t CK
READ or
WRITE
DON’T CARE
T3
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition