mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 19

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Operation
BANK/ROW ACTIVATION
Figure 6:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
Activating a Specific Row in a Specific Bank
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated. See Figure 6.
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
issued. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 7 on page 20, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
BA0, BA1
RRD.
A0–A11
RAS#
CAS#
WE#
CLK
CKE
CS#
HIGH
t
RCD (MIN)/
ADDRESS
ADDRESS
BANK
ROW
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
DON´T CARE
19
t
t
CK - 3. (The same procedure is used to convert other
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) should be divided by
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
RC.