mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 34

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 27:
Figure 28:
WRITE with Auto Precharge
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
READ With Auto Precharge Interrupted by a READ
READ With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
2. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
3. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is HIGH at T2 to prevent D
Internal
States
Internal
States
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 29 on page 35).
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 30 on page 35).
t
COMMAND
COMMAND
W
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
R is met, where
DQM
CLK
CLK
DQ
DQ
1
Active
Page
READ - AP
BANK n,
BANK n
Page Active
COL a
T0
NOP
T0
READ with Burst of 4
READ - AP
BANK n,
BANK n
Page Active
Page Active
COL a
T1
T1
NOP
CL = 3 (BANK n)
t
W
READ with Burst of 4
R begins when the WRITE to bank m is registered. The last
34
CL = 3 (BANK n)
T2
T2
OUT
NOP
NOP
a + 1 from contending with D
READ - AP
BANK m,
t
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T3
BANK m
COL d
T3
W
D
NOP
OUT
a
Interrupt Burst, Precharge
R is met, where
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
D
NOP
d
IN
CL = 3 (BANK m)
Interrupt Burst, Precharge
D
WRITE with Burst of 4
OUT
a
t
RP - BANK n
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
t
W
R begins when the READ to
T6
T6
d + 2
NOP
NOP
D
IN
D
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
OUT
d
Register Definition
IN
DON’T CARE
DON’T CARE
d at T4.
Idle
T7
T7
t WR - BANK m
d + 3
NOP
NOP
D
t RP - BANK m
IN
Precharge
Write-Back
D
d + 1
OUT
Idle