mt48lc4m32b2tg-7-it Micron Semiconductor Products, mt48lc4m32b2tg-7-it Datasheet - Page 47

• Manufacturer Part Number: mt48lc4m32b2tg-7-it
• Description: 128mb X32 Sdram
• Manufacturer: Micron Semiconductor Products

Notes
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. K 9/07 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once in any two-clock
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
23. The clock frequency must remain constant during access or precharge states (READ,
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO Refresh
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
biased at 1.4V. AC can range from 0pF to 6pF.
with minimum cycle time and the outputs open.
operation over the full temperature range (0°C ≤ T
IT parts) is ensured.
commands, before proper device operation is ensured. (V
ered up simultaneously. V
Refresh command wake-ups should be repeated any time the
ment is exceeded.
sit between V
Q
t
a reference to V
High-Z.
crossover point.
period and are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
mum cycle rate is slower as CL is reduced.
cannot be greater than one third of the cycle rate. V
for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the
cycle rate.
WRITE, including
data rate.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
IH
is dependent on output loading and cycle rates. Specified values are obtained
specifications are tested after the device is properly initialized.
overshoot: V
DD
current will decrease as CL is reduced. This is due to the fact that the maxi-
t
CK = 143 MHz for -7, 166 MHz for -6.
30pF
IH
OH
DD
and V
IH
t
or V
W
tests have V
(MAX) = V
R, and PRECHARGE commands). CKE may be used to reduce the
IL
OL
(or between V
. The last valid data element will meet
SS
t
47
SS
T = 1ns.
and V
t
t
t
.
DD
W
W
CKS; clock(s) specified as a reference only at minimum
DD
IL
R plus
R.
, V
Q + 1.2V for a pulse width ≤ 3ns, and the pulse width
= 0.25 and V
SS
DD
IH
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q = +3.3V; f = 1 MHz, T
or V
t
IL
RP; clock(s) specified as a reference only at
and V
IL
levels.
IH
IH
= 2.75, with timing referenced to 1.5V
) in a monotonic manner.
A
≤ +70°C and –40°C ≤ T
IL
undershoot: V
DD
©2001 Micron Technology, Inc. All rights reserved.
A
128Mb: x32 SDRAM
and V
= 25°C; pin under test
t
REF refresh require-
t
OH before going
DD
IL
Q must be pow-
(MIN) = –1.2V
A
≤ +85°C for
Notes